Maximizing cubic phase group III-nitride on patterned silicon

US10027086B2 · kind B2 · utility

Assignee

• BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS · US

Inventors

• Can Bayram · Champaign, US
• Richard Y. Liu · Woodbury, US

Key dates

• Filing date: Apr 18, 2017
• Grant date: Jul 17, 2018
• Expiry date: Apr 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H20/825
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.