Referenceless clock and data recovery circuits
US10027332B1 · kind B1 · utility
8Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Aug 7, 2017 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Aug 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.