Ethernet physical layer circuit and clock recovery method thereof
US10027468B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Aug 25, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An Ethernet physical layer circuit and a clock recovery method are provided. An analog-to-digital converter samples an analog input signal with a sampling clock to generate a digital input signal. A clock generator is coupled to the analog-to-digital converter, outputs the sampling clock to the analog-to-digital converter, and adjusts a phase of the sampling clock according to a phase control signal. The clock recovery circuit is coupled to the analog-to-digital converter and the clock generator, detects a timing error of the digital input signal at refresh stages in a lower energy consumption idle mode to obtain phase adjustment information, and generates the phase control signal based on the phase adjustment information at quiet stages in the low power idle mode. The clock generator correspondingly receives the phase control signal in the quiet stages to adjust the phase of the sampling clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.