Synchronization and training stage operation
US10027471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.