Chained packet sequences in a network on a chip architecture
US10027583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Aug 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.