Patent · US Active

Time-division multiplexing data aggregation over high speed serializer/deserializer lane

US10027600B2 · kind B2 · utility

2Cited by

9References

13Claims

0Family size

Assignee

Artesyn Embedded Computing, Inc. · US

Inventors

Stephan Kruecker · Unterhaching, DE
Armin Jacht · Munich, DE
Reinhold Hofer · Olching, DE

Key dates

Filing date	Sep 10, 2014
Grant date	Jul 17, 2018
Priority date	—
Expiry date	Sep 10, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH04J3/1623
WIPO fieldTelecommunications
WIPO sectorElectrical engineering

Abstract

A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.