Memory controller, and memory module and processor including the same
US10031676B2 · kind B2 · utility
2Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | Jul 13, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change memory, and a request queue stores the write request. A scheduler returns a completion on the write request to the CPU when a predetermined write time has elapsed. The predetermined write time is shorter than a write latency time that is taken to complete the data write to a memory cell of the memory device in response to the write request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.