Hierarchical processing for extended product codes
US10031701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Mar 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for hierarchical correction coding includes converting data for a storage system into w storage device arrays, each storage device array including n storage devices, and each storage device divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Erasures in the w storage device arrays are corrected based on protecting each row and column in each m×n array by an erasure-correcting code. Each group of t storage devices contains extra parities to correct extra erasures in addition to erasures corrected by vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.