Flash memory
US10031792B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.