Configurable reliability for memory devices
US10031801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Apr 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology relating to configurable reliability schemes for memory devices is disclosed. The technology includes a memory controller that selectively controls at least a type or an extent of a reliability scheme for at least a portion of a memory device. The technology also includes a computing device that can dynamically select and employ reliability schemes from a collection of different reliability schemes. A reliability scheme may be selected on a per-process, per-allocation request, per-page, per-cache-line, or other basis. The reliability schemes may include use of parity, use of data mirroring, use of an error correction code (ECC), storage of data without redundancy, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.