Address re-ordering mechanism for efficient pre-fetch training in an out-of order processor
US10031851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jan 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.