Memory system, storage device, and method for controlling memory system
US10031865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2015 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Oct 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.