Patent · US Active

Detecting circuit design flaws based on timing analysis

US10031995B2 · kind B2 · utility

1Cited by

4References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Wilhelm Haller · Winnenden, DE
Kurt Lind · Lörrach, DE
Friedrich Schroeder · Stuttgart, DE
Stefan Zimmermann · Laufenbürg, DE

Key dates

Filing date	Sep 18, 2015
Grant date	Jul 24, 2018
Priority date	—
Expiry date	Mar 10, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.