Timing based net constraints tagging with zero wire load validation
US10031996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.