Solid-state electrolytic capacitor manufacturing method and solid-state electrolytic capacitor
US10032567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G13/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A solid electrolytic capacitor having grooves provided in a valve-acting metal substrate that includes a porous surface part and a non-porous body part, the bottoms of the grooves being non-porous. The valve-acting metal substrate is divided into a plurality of unit regions by the grooves, and define cathode layer formation parts in the porous surface parts for each unit region. A dielectric layer covers the surfaces of the cathode layer formation parts of the valve-acting metal substrate and the grooves between the cathode layer formation parts. A solid electrolyte layer and a cathode extraction layer cover the surface of the dielectric layer, thereby providing a sheet in which a plurality of solid electrolytic capacitor elements are prepared integrally with the grooves interposed therebetween. The sheet is cut at the grooves, and a dielectric layer is formed on the cut surfaces located around the cathode layer formation parts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.