FinFET with ESD protection
US10032764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Sep 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.