Semiconductor device and method of manufacturing semiconductor device
US10032785B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pair of floating gates disposed to be spaced apart from each other by a first distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a memory region. Also, a pair of floating gates disposed to be spaced apart from each other by a second distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a monitor region. Then, the second distance is smaller than the first distance. Thus, by narrowing a distance between the floating gates in the monitor region, a tapered portion can be provided on a side surface portion of the floating gate in the monitor region. Then, by checking this tapered portion, it is possible to understand the shape of the floating gate in the memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.