Method for synchronously distributing a digital signal over N identical adjacent blocks of an integrated circuit
US10033363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention proposes a method for distributing a signal to each block Bj of a series of N adjacent blocks of identical design in an electronic circuit. It proposes, in an identical fashion for each of the N blocks, placing a timing delay circuit MUX-DELj on the path for conveying a signal Sc from the input INcj of the block to an internal electrical node Ndj of the block for this signal Sc; providing for the timing delay circuit to supply N delayed signals corresponding to N different timing delays Δf1, . . . Δfj, . . . ΔfN separated by an increment of elementary duration Δt that corresponds to the elementary delay Δt for transit of a block introduced into a conductive line; and selecting the delayed signal corresponding to the applicable timing delay according to the block in question, by means of an index signal propagated through the N blocks, and which is incremented or decremented on passage through each block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.