Low power compact peak detector with improved accuracy
US10033364B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/302
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.