Stacked synthesizer for wide local oscillator generation using a dynamic divider
US10033393B2 · kind B2 · utility
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4References
17Claims
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Key dates
| Filing date | Jan 10, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jan 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.