Low power analog to digital converter
US10033402B2 · kind B2 · utility
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10References
28Claims
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Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.