C-PHY half-rate clock and data recovery adaptive edge tracking
US10033519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.