Equalizer circuit optimization using coarse frequency detection
US10033555B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03764
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system can be configured to control an equalizer circuit to equalize a data signal without requiring prior knowledge of the data signal's data rate. In an example, the system includes an equalizer circuit configured to equalize a data signal based on an equalizer control signal to produce an equalized signal, and a pattern detector configured to detect a specified data pattern in the equalized signal at each of multiple sampling rates. A control circuit can be configured to generate a preferred equalization control signal based on a sampling rate, selected from the multiple sampling rates, at which the pattern detector detects the specified data pattern in the equalized signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.