Selective partitioning of via structures in printed circuit boards
US10034391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2014 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0713
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.