Compute through power loss approach for processing device having nonvolatile logic memory
US10037071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2015 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.