Chip power supply method and chip
US10037072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.