Virtualization of hardware accelerator allowing simultaneous reading and writing
US10037222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2013 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jan 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally provided to virtualize hardware acceleration. In some examples, a coprovisor component may be configured to multiplex multiple domains' requests to access a hardware accelerator such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a comparable accelerator in a paravirtualized environment. Hyper-requesting may be employed for hardware acceleration virtualization, where a hardware acceleration module concurrently loads a portion of data of a request for a first accelerator application and a portion of data of another request for a second accelerator application and simultaneously processes the two portions of data. Directly situated on a device driver layer, the coprovisor may schedule portions of access requests to the hardware accelerator at the same time through direct memory access (DMA) context switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.