Adaptive debug tracing for microprocessors
US10037259B2 · kind B2 · utility
2Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Oct 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.