Test suite minimization
US10037264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and system for classifying test cases. In one implementation, the method comprises creating a test step master list comprising a plurality of test case, one more test step associated with the plurality of test case, and a test step identification number associated with the one more test step. Further, the method comprises generating a sequence diagram for each of the plurality of test cases based on the test step master list. Furthermore, the method comprises classifying, by the processor, each of the plurality of test cases in to an independent test case or an asynchronous test case or a synchronous test case based on the sequence diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.