Operation processing device having hierarchical cache memory and method for controlling operation processing device having hierarchical cache memory
US10037278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jan 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation processing device including: processors, first cache corresponding to each processors; and a second cache shared by the processors, wherein the second cache includes; a data retaining unit that retains data, a first information retaining unit that retains first management information of data in the first cache, a second information retaining unit that retains second management information of data in the data retaining unit, a classifying unit that classifies a request performed by referencing the first management information and not referencing the second management information as a first type request and classifies a request performed by referencing the second management information as a second type request, a second processing unit that references the second management information to perform the second type request, and a first processing unit that references the first management information and does not reference the second management information to perform the first type request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.