Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same
US10037401B2 · kind B2 · utility
1Cited by
11References
19Claims
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Key dates
| Filing date | Feb 14, 2018 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.