Optimized multi gain LNA enabling low current and high linearity including highly linear active bypass
US10038418B1 · kind B1 · utility
15Cited by
2References
9Claims
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Key dates
| Filing date | Apr 4, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Apr 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.