High-speed soft-edge sense-amplifier-based flip-flop
US10038429B1 · kind B1 · utility
2Cited by
8References
22Claims
0Family size
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Key dates
| Filing date | Aug 22, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.