Hierarchical statisically multiplexed counters and a method thereof
US10038448B2 · kind B2 · utility
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13References
17Claims
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Key dates
| Filing date | Jul 5, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Feb 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.