Decision feedback equalizer with post-cursor non-linearity correction
US10038575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2017
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a DFE including: an input terminal configured to receive an input signal carrying a plurality of symbols; an adder circuit coupled to the input terminal of the DFE; a plurality of comparator circuits configured to receive respective threshold signals; a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, where: the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and the plurality of correction coefficients are independently adjusted based on a previously received symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.