Methods and apparatuses for advanced receiver design
US10039017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M2207/206
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are embodiments of apparatuses and methods of use thereof for frequency domain (FD) chip level (CL) equalizers used in wireless receivers. The FD-CL-EQ may further selectively apply a higher order matrix inverse or a lower order matrix inverse in the calculation of a channel estimate based on whether interference is present or not. Further disclosed are embodiments of methods and apparatuses for estimating pilot signal-to-interference ratio (SIR) in the wireless receivers. Further disclosed are methods and apparatuses for compensating for phase errors in received demodulated data symbols to improve performance of the wireless receivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.