GOA circuit
US10043477B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jan 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a GOA circuit, using the ninth and tenth TFTs and the resistor to control the voltage level of the third node, wherein ninth TFT having the gate connected to the m-th clock signal, the source connected to the first constant voltage, and the drain connected to one end of the resistor; the tenth TFT having the gate connected to the (m+2)-th clock signal, the source connected to the second constant voltage, and the drain connected to the other end of the resistor. Through the m-th and the (m+2)-th clock signal to control the ninth and the tenth TFTs to become conductive alternately, the present invention can charge and discharge the third node regularly to prevent the threshold voltage shift of the key TFT because the third node stays high for extended time, and ensure the stability of GOA circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.