Semiconductor memory device
US10043817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jul 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.