Array substrate and the manufacturing methods thereof
US10043912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2203/04103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure relates to an array substrate and the manufacturing method thereof. The array substrate includes a glass substrate. The shading metal layer and the buffering layer are formed on the glass substrate in sequence. The TFT layer is formed on the buffering layer, and the TFT is arranged above the shading metal layer. The insulation layer and the organic layer are formed on the TFT layer in sequence. In addition, the pixel electrode layer connects to the source/drain of the TFT via the first through hole. The touch electrode layer connects to the shading metal layer via the second through hole. The passivation layer is configured between the pixel electrode layer and the touch electrode layer. In this way, the manufacturing process is simplified, and the coupling capacitance between the touch electrode and the signal line may be effectively reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.