Thin-film transistor having channel structure with increased width-length ratio
US10043916B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 28, 2015 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6736
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention disclose a thin-film transistor having a channel structure that has an increased width-length ratio and a manufacturing method thereof, a display substrate and a display device. The thin-film transistor comprises a gate, a gate insulation layer and an active layer stacked on a substrate, the active layer is formed therein with a source region, a drain region and a channel region, a surface of the active layer facing the gate insulation layer is at least partially formed with a non-planar surface in the channel region, such that the non-planar surface of the active layer has a tortuous shape in a width direction of the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.