Power amplifier and gain reduction circuit thereof
US10044334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Dec 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.