Low-power slew rate detector for edge rate control of an output power stage
US10044346B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for determining a slew rate of an input signal includes a first MOSFET, a second MOSFET, and a resistor coupled in series between a ground terminal and a power terminal. The resistor is coupled between the power terminal and the second MOSFET, and the first MOSFET is coupled between the second MOSFET and the ground. The second MOSFET is coupled to a bias circuit to provide a bias current. The circuit also includes a capacitor having a first terminal and a second terminal, the first terminal coupled to the input signal and the second terminal coupled to the gate terminal and the drain terminal of the first MOSFET. A current flowing through the MOSFET during changes in the input signal represents a slew rate of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.