Packet retransmission and memory sharing
US10044473B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5647
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system that includes a multicarrier transceiver including a processor and memory. The system transmitting a packet using a forward error correction encoder and an interleaver, wherein the packet comprises a header field and a plurality of bytes, and wherein the header field comprises a sequence identifier (SID) and receiving at least one message using a forward error correction decoder and without using a deinterleaver, wherein the at least one message is received in a single DMT symbol and wherein the at least one message includes an acknowledgement (ACK) or a negative acknowledgement (NACK) of the transmitted packet. An SNR margin of the at least one message is greater than an SNR margin of the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.