Systems and methods for efficiently storing packet data in network switches
US10044646B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2014 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9031
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network switch allocates large-scale memory units as data packets are received in order to implement per-queue, circular egress buffers. Each large-scale memory unit is larger than the maximum packet length of the received packets and is capable of storing a plurality of data packets, thereby reducing the number of memory allocation events that are required to process a given number of data packets. Efficient techniques for writing to and reading from the large-scale egress memory units have been developed and may be used to reduce processing delays. Such techniques are compatible with relatively inexpensive memory devices, such as dynamic random access memory (DRAM), that may be separate from the circuitry used to process the data packets. The described architectures are easily scalable so that that a large number of ports (e.g., thousands) may be implemented at a relatively low cost and complexity without introducing significant processing delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.