Method for capturing an image with dark current reduction and low power consumption
US10044934B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2015 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Mar 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/7795
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for capturing an image in an image sensor with a matrix of rows and columns of active pixels, powered between a first power supply terminal at zero potential (Vss) and a second power supply terminal at a positive power supply potential (Vdd). Each pixel comprises a photodiode and a gate for transferring the photogenerated charges to a charge storage node. A negative potential (VNEG) is applied to the transfer gate by a charge pump during the charge integration time and it receives a transfer control signal (TRA) common to all the pixels during a transfer time window. The transfer or reset control signal successively comprises at least one first phase during which it goes from the negative potential (VNEG) to a positive transfer potential, a second phase during which it goes from the positive transfer potential to the zero potential supplied by the first power supply terminal, a third phase of finite duration during which it remains at the zero potential, and a fourth phase in which it goes back from the zero potential to the negative potential supplied by the charge pump. Going through the power supply potential limits the current demands in the ch…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.