In-pixel digital gain and offset corrections
US10044958B1 · kind B1 · utility
2Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/79
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method includes correcting for at least one of gain and offset during frame integration for photodetector events. Gain and offset correction is performed separately in each pixel of a digital read-out integrated circuit (DROIC) for a plurality of corresponding pixels in a photodetector array. First and second binary counters respectively use a gain register and an offset register to implement gain and offset correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.