Array substrate, manufacturing method thereof and display device
US10048555B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Oct 1, 2014 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/121
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes: a first metal area disposed at an edge portion of the array substrate and electrically connected with a common electrode line or common electrodes; a second metal area disposed at the edge portion of the array substrate, corresponding to and insulated from the first metal area, and configured for access of a stabilized voltage that is a fixed voltage. At least one capacitor is formed by the first metal area and the second metal area. The array substrate can obtain more stable pixel common electrode voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.