Array substrate and semiconductor device containing the same, and method for fabricating the same
US10048559B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Oct 10, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides an array substrate. The array substrate includes a substrate having a display region with a plurality of pixel regions, each pixel region having two or more first regions; a common electrode line between two adjacent pixel regions; a gate line; a data line intersecting with the gate line; at least one of the gate line and the data line being in a second region between two adjacent first regions; and a pixel electrode having a hollowed-out pattern within a corresponding first region, pixel electrodes corresponding to the two or more first regions being a pixel electrode unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.