Managing power consumption of a gated clock mesh
US10048739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Feb 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power consumption of an integrated circuit (IC) clock mesh can be managed by a method of clock mesh design. Clock mesh data, including a location of a set of circuit elements and gating information of the set of circuit elements of the clock mesh, can be retrieved. A portion of the clock mesh, known as a local clock mesh, can be identified by analyzing the clock mesh data. The local clock mesh can include a subset of circuit elements having substantially similar clock gating characteristics, and which satisfy a placement density threshold. Mesh clock gating (MCG) cells can be added to wires surrounding the perimeter of the local mesh. MCG cells can be configured to enable and disable clock loads and clock mesh wires within the local clock mesh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.