Electronic system with memory data protection mechanism and method of operation thereof
US10049004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | May 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system includes: a host processor; a system memory, coupled to the host processor, includes data persistence regions identified by the host processor; a non-volatile storage device, including a fast path write (FPW) reserved area, configured to store user data from the system memory in a non-volatile media; and a power monitor unit, coupled to the host processor, configured to detect a power loss by a primary power failure detector and assert a power-loss detection control; and wherein the host processor is configured to engage a RAM flush driver for moving the content of the data persistence regions to a fast path write (FPW) reserved area in the non-volatile media when the power-loss detection control is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.